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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICH_VMCR, Virtual Machine Control Register</h1><p>The GICH_VMCR characteristics are:</p><h2>Purpose</h2>
        <p>Enables the hypervisor to save and restore the virtual machine view of the GIC state. This register is updated when a virtual machine updates the virtual CPU interface registers.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GICv3_LEGACY is implemented and EL2 is implemented. Otherwise, direct accesses to GICH_VMCR are <span class="arm-defined-word">RES0</span>.</p>
        <p>This register is available when the GIC implementation supports interrupt virtualization.</p>
      <h2>Attributes</h2>
        <p>GICH_VMCR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="8"><a href="#fieldset_0-31_24">VPMR</a></td><td class="lr" colspan="3"><a href="#fieldset_0-23_21">VBPR0</a></td><td class="lr" colspan="3"><a href="#fieldset_0-20_18">VBPR1</a></td><td class="lr" colspan="8"><a href="#fieldset_0-17_10">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">VEOIM</a></td><td class="lr" colspan="4"><a href="#fieldset_0-8_5">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-4_4">VCBPR</a></td><td class="lr" colspan="1"><a href="#fieldset_0-3_3">VFIQEn</a></td><td class="lr" colspan="1"><a href="#fieldset_0-2_2">VAckCtl</a></td><td class="lr" colspan="1"><a href="#fieldset_0-1_1">VENG1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">VENG0</a></td></tr></tbody></table><h4 id="fieldset_0-31_24">VPMR, bits [31:24]</h4><div class="field"><p>Virtual priority mask. The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.</p>
<p>This alias field is updated when a VM updates <a href="ext-gicv_pmr.html">GICV_PMR</a>.Priority.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-23_21">VBPR0, bits [23:21]</h4><div class="field"><p>Virtual Binary Point Register, Group 0. Defines the point at which the priority value fields split into two parts, the Group priority field and the subpriority field. The Group priority field determines Group 0 interrupt preemption, and also determines Group 1 interrupt preemption if GICH_VMCR.VCBPR == 1.</p>
<p>This alias field is updated when a VM updates <a href="ext-gicv_bpr.html">GICV_BPR</a>.Binary_Point.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-20_18">VBPR1, bits [20:18]</h4><div class="field"><p>Virtual Binary Point Register, Group 1. Defines the point at which the priority value fields split into two parts, the Group priority field and the subpriority field. The Group priority field determines Group 1 interrupt preemption if GICH_VMCR.VCBPR == 0.</p>
<p>This alias field is updated when a VM updates <a href="ext-gicv_abpr.html">GICV_ABPR</a>.Binary_Point.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-17_10">Bits [17:10]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-9_9">VEOIM, bit [9]</h4><div class="field">
      <p>Virtual EOImode. Possible values of this bit are:</p>
    <table class="valuetable"><tr><th>VEOIM</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>A write of an INTID to <a href="ext-gicv_eoir.html">GICV_EOIR</a> or <a href="ext-gicv_aeoir.html">GICV_AEOIR</a> drops the priority of the interrupt with that INTID, and also deactivates that interrupt.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>A write of an INTID to <a href="ext-gicv_eoir.html">GICV_EOIR</a> or <a href="ext-gicv_aeoir.html">GICV_AEOIR</a> only drops the priority of the interrupt with that INTID. Software must write to <a href="ext-gicv_dir.html">GICV_DIR</a> to deactivate the interrupt.</p>
        </td></tr></table>
      <p>This alias field is updated when a VM updates <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EOImode.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-8_5">Bits [8:5]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-4_4">VCBPR, bit [4]</h4><div class="field">
      <p>Virtual Common Binary Point Register. Possible values of this bit are:</p>
    <table class="valuetable"><tr><th>VCBPR</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p><a href="ext-gicv_abpr.html">GICV_ABPR</a> determines the preemption group for Group 1 interrupts.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p><a href="ext-gicv_bpr.html">GICV_BPR</a> determines the preemption group for Group 1 interrupts.</p>
        </td></tr></table>
      <p>This alias field is updated when a VM updates <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.CBPR.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-3_3">VFIQEn, bit [3]</h4><div class="field">
      <p>Virtual FIQ enable. Possible values of this bit are:</p>
    <table class="valuetable"><tr><th>VFIQEn</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Group 0 virtual interrupts are presented as virtual IRQs.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Group 0 virtual interrupts are presented as virtual FIQs.</p>
        </td></tr></table>
      <p>This alias field is updated when a VM updates <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.FIQEn.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-2_2">VAckCtl, bit [2]</h4><div class="field">
      <p>Virtual AckCtl. Possible values of this bit are:</p>
    <table class="valuetable"><tr><th>VAckCtl</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>If the highest priority pending interrupt is Group 1, a read of <a href="ext-gicv_iar.html">GICV_IAR</a> or <a href="ext-gicv_hppir.html">GICV_HPPIR</a> returns an INTID of 1022.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>If the highest priority pending interrupt is Group 1, a read of <a href="ext-gicv_iar.html">GICV_IAR</a> or <a href="ext-gicv_hppir.html">GICV_HPPIR</a> returns the INTID of the corresponding interrupt.</p>
        </td></tr></table><p>This alias field is updated when a VM updates <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.AckCtl.</p>
<p>This field is supported for backwards compatibility with GICv2. Arm deprecates the use of this field.</p><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-1_1">VENG1, bit [1]</h4><div class="field">
      <p>Virtual interrupt enable, Group 1. Possible values of this bit are:</p>
    <table class="valuetable"><tr><th>VENG1</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Group 1 virtual interrupts are disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Group 1 virtual interrupts are enabled.</p>
        </td></tr></table>
      <p>This alias field is updated when a VM updates <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EnableGrp1.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-0_0">VENG0, bit [0]</h4><div class="field">
      <p>Virtual interrupt enable, Group 0. Possible values of this bit are:</p>
    <table class="valuetable"><tr><th>VENG0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Group 0 virtual interrupts are disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Group 0 virtual interrupts are enabled.</p>
        </td></tr></table>
      <p>This alias field is updated when a VM updates <a href="ext-gicv_ctlr.html">GICV_CTLR</a>.EnableGrp0.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="text_after_fields">
    <div class="note"><span class="note-header">Note</span>
      <p>A List register is in the pending state only if the corresponding <a href="ext-gich_lrn.html">GICH_LR&lt;n&gt;</a> value is <span class="binarynumber">0b01</span>, that is, pending. The active and pending state is not included.</p>
    </div>
  </div><h2>Accessing GICH_VMCR</h2>
        <p>This register is used only when System register access is not enabled. When System register access is enabled:</p>

      
        <ul>
<li>For AArch32 implementations, <a href="AArch32-ich_vmcr.html">ICH_VMCR</a> provides equivalent functionality.
</li><li>For AArch64 implementations, <a href="AArch64-ich_vmcr_el2.html">ICH_VMCR_EL2</a> provides equivalent functionality.
</li></ul>
      <h4>GICH_VMCR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Virtual interface control</td><td><span class="hexnumber">0x0008</span></td><td>GICH_VMCR</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When GICD_CTLR.DS == 0, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Secure, accesses to this register are <span class="access_level">RW</span>.
          </li><li>When an access is Non-secure, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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